Sdc

the module hasn’t doc yet.

• current_design

• get_ports

• all_inputs

• all_outputs

• get_cells

• get_pins

• get_nets

• get_libs

• get_lib_cells

• get_lib_pins

• all_registers

• get_clocks

• all_clocks

• create_clock

• set_drive

• set_driving_cell

• set_fanout_load

• set_input_transition

• set_load

• set_port_fanout_number

• set_input_delay

• set_output_delay

• set_logic_dc

• set_logic_one

• set_logic_zero

• set_case_analysis

• remove_case_analysis

• set_max_capacitance

• set_min_capacitance

• set_max_fanout

• set_max_transition

• set_false_path

• set_max_delay

• set_min_delay

• set_multicycle_path

• set_max_area

• create_generated_clock

• set_clock_latency

• set_clock_uncertainty

• set_clock_transition

• set_wire_load_model

• set_wire_load_mode

• set_wire_load_selection_group

• set_clock_gating_check

• set_sense

• set_data_check

• set_disable_timing

• set_clock_groups

• set_min_pulse_width

• set_max_time_borrow

• set_wire_load_min_block_size

• set_ideal_network

• set_ideal_latency

• set_ideal_transition

• set_propagated_clock

• set_resistance

• set_timing_derate

• group_path

• update_timing

• characterize

• write_sdc

• remove_propagated_clock

• set_disable_clock_gating_check

• set_operating_conditions

• set_units

• set_hierarchy_separator