Sdc
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
the module hasn't doc yet.



* :doc:`cmds/current_design`
* :doc:`cmds/get_ports`
* :doc:`cmds/all_inputs`
* :doc:`cmds/all_outputs`
* :doc:`cmds/get_cells`
* :doc:`cmds/get_pins`
* :doc:`cmds/get_nets`
* :doc:`cmds/get_libs`
* :doc:`cmds/get_lib_cells`
* :doc:`cmds/get_lib_pins`
* :doc:`cmds/all_registers`
* :doc:`cmds/get_clocks`
* :doc:`cmds/all_clocks`
* :doc:`cmds/create_clock`
* :doc:`cmds/set_drive`
* :doc:`cmds/set_driving_cell`
* :doc:`cmds/set_fanout_load`
* :doc:`cmds/set_input_transition`
* :doc:`cmds/set_load`
* :doc:`cmds/set_port_fanout_number`
* :doc:`cmds/set_input_delay`
* :doc:`cmds/set_output_delay`
* :doc:`cmds/set_logic_dc`
* :doc:`cmds/set_logic_one`
* :doc:`cmds/set_logic_zero`
* :doc:`cmds/set_case_analysis`
* :doc:`cmds/remove_case_analysis`
* :doc:`cmds/set_max_capacitance`
* :doc:`cmds/set_min_capacitance`
* :doc:`cmds/set_max_fanout`
* :doc:`cmds/set_max_transition`
* :doc:`cmds/set_false_path`
* :doc:`cmds/set_max_delay`
* :doc:`cmds/set_min_delay`
* :doc:`cmds/set_multicycle_path`
* :doc:`cmds/set_max_area`
* :doc:`cmds/create_generated_clock`
* :doc:`cmds/set_clock_latency`
* :doc:`cmds/set_clock_uncertainty`
* :doc:`cmds/set_clock_transition`
* :doc:`cmds/set_wire_load_model`
* :doc:`cmds/set_wire_load_mode`
* :doc:`cmds/set_wire_load_selection_group`
* :doc:`cmds/set_clock_gating_check`
* :doc:`cmds/set_sense`
* :doc:`cmds/set_data_check`
* :doc:`cmds/set_disable_timing`
* :doc:`cmds/set_clock_groups`
* :doc:`cmds/set_min_pulse_width`
* :doc:`cmds/set_max_time_borrow`
* :doc:`cmds/set_wire_load_min_block_size`
* :doc:`cmds/set_ideal_network`
* :doc:`cmds/set_ideal_latency`
* :doc:`cmds/set_ideal_transition`
* :doc:`cmds/set_propagated_clock`
* :doc:`cmds/set_resistance`
* :doc:`cmds/set_timing_derate`
* :doc:`cmds/group_path`
* :doc:`cmds/update_timing`
* :doc:`cmds/characterize`
* :doc:`cmds/write_sdc`
* :doc:`cmds/remove_propagated_clock`
* :doc:`cmds/set_disable_clock_gating_check`
* :doc:`cmds/set_operating_conditions`
* :doc:`cmds/set_units`
* :doc:`cmds/set_hierarchy_separator`


.. toctree::
   :hidden:

   cmds/current_design
   cmds/get_ports
   cmds/all_inputs
   cmds/all_outputs
   cmds/get_cells
   cmds/get_pins
   cmds/get_nets
   cmds/get_libs
   cmds/get_lib_cells
   cmds/get_lib_pins
   cmds/all_registers
   cmds/get_clocks
   cmds/all_clocks
   cmds/create_clock
   cmds/set_drive
   cmds/set_driving_cell
   cmds/set_fanout_load
   cmds/set_input_transition
   cmds/set_load
   cmds/set_port_fanout_number
   cmds/set_input_delay
   cmds/set_output_delay
   cmds/set_logic_dc
   cmds/set_logic_one
   cmds/set_logic_zero
   cmds/set_case_analysis
   cmds/remove_case_analysis
   cmds/set_max_capacitance
   cmds/set_min_capacitance
   cmds/set_max_fanout
   cmds/set_max_transition
   cmds/set_false_path
   cmds/set_max_delay
   cmds/set_min_delay
   cmds/set_multicycle_path
   cmds/set_max_area
   cmds/create_generated_clock
   cmds/set_clock_latency
   cmds/set_clock_uncertainty
   cmds/set_clock_transition
   cmds/set_wire_load_model
   cmds/set_wire_load_mode
   cmds/set_wire_load_selection_group
   cmds/set_clock_gating_check
   cmds/set_sense
   cmds/set_data_check
   cmds/set_disable_timing
   cmds/set_clock_groups
   cmds/set_min_pulse_width
   cmds/set_max_time_borrow
   cmds/set_wire_load_min_block_size
   cmds/set_ideal_network
   cmds/set_ideal_latency
   cmds/set_ideal_transition
   cmds/set_propagated_clock
   cmds/set_resistance
   cmds/set_timing_derate
   cmds/group_path
   cmds/update_timing
   cmds/characterize
   cmds/write_sdc
   cmds/remove_propagated_clock
   cmds/set_disable_clock_gating_check
   cmds/set_operating_conditions
   cmds/set_units
   cmds/set_hierarchy_separator