set_sim_clk
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

`-port`_
 Specify the clk port to configure


`-frequency`_
 Specify the output duty cycle, the value is [0, 1]


`-phase`_
 Specifies the clock tick on which the clk depends


`-unit`_
 specify the bus width when data is a bus


`-adverse`_
 Specifies the clock tick on which the input depends




-----------------

.. _set_sim_clk-port:

-port
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

| Specify the clk port to configure

**attribute**

:type: STRING
:positional: True
:default: 

**related_options**



**simple case**

    There is currently no simple case.




-----------------

.. _set_sim_clk-frequency:

-frequency
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

| Specify the output duty cycle, the value is [0, 1]

**attribute**

:type: FLOAT
:positional: True
:default: 

**related_options**



**simple case**

    There is currently no simple case.




-----------------

.. _set_sim_clk-phase:

-phase
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

| Specifies the clock tick on which the clk depends

**attribute**

:type: FLOAT
:positional: False
:default: 0

**related_options**



**simple case**

    There is currently no simple case.




-----------------

.. _set_sim_clk-unit:

-unit
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

| specify the bus width when data is a bus

**attribute**

:type: STRING
:positional: False
:default: KHz

**related_options**



**simple case**

    There is currently no simple case.




-----------------

.. _set_sim_clk-adverse:

-adverse
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

| Specifies the clock tick on which the input depends

**attribute**

:type: BOOL
:positional: False
:default: 

**related_options**



**simple case**

    There is currently no simple case.