set_black_box
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

`-work`_
 library where the unit(s)/module(s) is analyzed(elaborated)


`-module`_
 name of Verilog module to black box




-----------------

.. _set_black_box-work:

-work
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

| library where the unit(s)/module(s) is analyzed(elaborated)

**attribute**

:type: STRING
:positional: False
:default: 

**related_options**



**simple case**

    There is currently no simple case.




-----------------

.. _set_black_box-module:

-module
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

| name of Verilog module to black box

**attribute**

:type: STRLIST
:positional: False
:default: 

**related_options**



**simple case**

    There is currently no simple case.